Графический процессор SPC5645SF0VVU панели приборов Nissan Murano III (Z52) 2014

Цена: 8 000 руб.
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В нашем интернет магазине Вы можете купить графический процессор SPC564SVVU панели приборов Nissan Murano III (Z52) 2014 производства Freescale Semiconductor по оптимальной стоимости, а так ж воспользоваться услугой по ремонту приборной панели Nissan Murano III (Z52) 2014

Список функций • Dual-issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z4d) — Memory Management Unit (MMU) — 4 KB, 2/4-way instruction cache • 2 MB on-chip ECC flash memory with: — Flash memory controller — Prefetch buffers • 64 KB on-chip ECC SRAM • 1 MB on-chip non-ECC graphics SRAM with two-port graphics SRAM controller • Memory Protection Unit (MPU) with up to 16 region descriptors and 32-byte region granularity to provide basic memory access permission and ensure separation between different codes and data • Interrupt Controller (INTC) with 181 peripheral interrupt sources and eight software interrupts • Two Frequency-Modulated Phase-Locked Loops (FMPLLs) — Primary FMPLL (FMPLL0) provides a system clock up to 125 MHz — Auxiliary FMPLL (FMPLL1) is available for use as an alternate, modulated or non-modulated clock source to eMIOS modules, QuadSPI and as alternate clock to the DCU and DCU-Lite for pixel clock generation • Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus masters • 16-channel Enhanced Direct Memory Access controller (eDMA) with multiple transfer request sources using a DMA channel multiplexer • Boot Assist Module (BAM) with 8 KB dedicated ROM for embedded boot code supports boot options including download of boot code via a serial link (CAN or SCI) • Two Display Control Units (DCU3 and DCULite) for direct drive of up to two TFT LCD displays up to XGA resolution • Timing Controller (TCON) and RSDS interface for the DCU3 module • 2D OpenVG 1.1 and raster graphics accelerator (GFX2D) • Video Input Unit (VIU2) supporting 8/10-bit ITU656 video input, YUV to RGB conversion, video down-scaling, de-interlacing, contrast adjustment and brightness adjustment. • DRAM controller supporting DDR1, DDR2, and LPDDR1 DRAMs • Stepper Motor Controller (SMC) — High-current drivers for up to six instrument cluster gauges driven in full dual H-bridge configuration — Stepper motor return-to-zero and stall detection module — Stepper motor short circuit detection • Sound Generator Module (SGM) — 4-channel mixer — Supports PCM wave playback and synthesized tones — Optional PWM or I2S outputs • Two 16-channel Enhanced Modular Input Output System (eMIOS) modules — Support a range of 16-bit Input Capture, Output Compare, Pulse Width Modulation and Quadrature Decode functions • 10-bit Analog-to-Digital Converter (ADC) with a maximum conversion time of 1 s — Up to 20 internal channels — Up to 8 external channels • Three Deserial Serial Peripheral Interface (DSPI) modules for full-duplex, synchronous, communications with external devices • QuadSPI serial flash memory controller — Supports single, dual and quad IO serial flash memory — Interfaces to external, memory-mapped serial flash memories — Supports simultaneous addressing of 2 external serial flashes to achieve up 80 MB/s read bandwidth • RLE decoder supporting memory to memory decoding of RLE data in conjunction with eDMA • Four local interconnect network (LINFlex) controller modules — Capable of autonomous message handling (master), autonomous header handling (slave mode), and UART support — Compliant with LIN protocol rev 2.1 • Three controller-area network (FlexCAN) modules — Compliant with the CAN protocol version 2.0 C — 64 configurable buffers — Programmable bit rate of up to 1 Mb/s • Four Inter-Integrated Circuit (I2C) internal bus controllers with master/slave bus interface • Low-power loop controlled pierce crystal oscillator supporting 4–16MHz external crystal or resonator • Real Time Counter (RTC) with clock source from internal 128 kHz or 16 MHz oscillator supporting autonomous wake-up with 1 ms resolution with maximum timeout of 2 seconds — Support for real time counter (RTC) with clock source from external 32 KHz crystal oscillator, supporting wake-up with 1 s resolution and maximum timeout of one hour — RTC optionally clocked by fast 4–16 MHz external oscillator • System timers: — Four-channel 32-bit System Timer Module (STM) — Eight-channel 32-bit Periodic Interrupt Timer (PIT) module (including ADC trigger) — Software Watchdog Timer (SWT) • System Integration Unit Lite (SIUL) module to manage external interrupts, GPIO and pad control • System Status and Configuration Module (SSCM) — Provides information for identification of the device, last boot mode, or debug status — Provides an entry point for the censorship password mechanism • Clock Generation Module (MC_CGM) to generate system clock sources and provide a unified register interface, enabling access to all clock sources • Clock Monitor Unit (CMU) — Monitors the integrity of the fast (4–16 MHz) external crystal oscillator and the primary FMPLL (FMPLL0) — Acts as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock • Mode Entry Module (MC_ME) — Controls the device power mode, i.e., RUN, HALT, STOP, or STANDBY — Controls mode transition sequences — Manages the power control, voltage regulator, clock generation and clock management modules • Power Control Unit (MC_PCU) to implement standby mode entry/exit and control connections to power domains • Reset Generation Module (MC_RGM) to manage reset assertion and release to the device at initial power-up • Nexus Development Interface (NDI) per IEEE-ISTO 5001-2008 Class 3 standard with additional Class 4 features: — Watchpoint Triggering — Processor Overrun Control • Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) • On-chip voltage regulator controller for regulating the 3.3–5 V supply voltage down to 1.2 V for core logic (requires external ballast transistor) • Package:1 — 176 LQFP, 0.5 mm pitch, 24 mm  24 mm outline — 208 LQFP, 0.5 mm pitch, 28 mm*28 mm outline — 416 TEPBGA, 1mm ball pitch, 27 mm*27 mm outline 

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