Логический драйвер TPIC6C596 панели приборов Dodge Caliber I 2006-2009
Характеристики
Параметр | Значение |
---|---|
Артикул | 016752 |
Модель и марка | Dodge Caliber I 2006-2009 |
Количество на складе | уточняйте у менеджера |
Количество просмотров | 333 |
Описание
В нашем интернет магазине Вы можете купить логический драйвер TPIC6C596 панели приборов Dodge Caliber I 2006-2009 производства Nexperia, а так же воспользоваться ремонтом приборной панели Dodge Caliber I 2006-2009
- LowrDS(on)...7ΩTyp
- Avalanche Energy . . . 30 mJ
- Eight Power DMOS Transistor Outputs of 100-mA Continuous Current
- 250-mA Current Limit Capability
- ESD Protection . . . 2500 V
- Output Clamp Voltage . . . 33 V
- Enhanced Cascading for Multiple Stages D All Registers Cleared With Single Input D Low Power Consumption
description
The TPIC6C596 is a monolithic, medium-voltage, low-current power 8-bit shift register designed for use in systems that require relatively moderate load power such as LEDs. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other low-current or medium-voltage loads.
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift register clock (SRCK) and the register clock (RCK), respectively. The storage register trans- fers data to the output buffer when shift register clear (CLR) is high. When CLR is low, all registers in the device are cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference.
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